Simple RISC machine
Using VHDL and an FPGA to design and test a simple RISC (Reduced Instruction Set Computer) machine from scratch.
Overview
In this project, I designed and implemented a simple RISC machine in a 16-bit architecture using Systems Verilog as my hardware description language. I used ModelSim to write testbenches and simulate the design, and Quartus to synthesize my design onto an FPGA board. The design includes everything you would find in a normal computer, such as an ALU, registers, memory, control units, and I/O functionality. The RISC machine has a noticable resemblance to the ARM ISA, but with a much simpler instruction set.
Step 1 – Datapath
First I started by building the datapath. The datapath consists of smaller modules such as the ALU, registers, multiplexers, a shifter unit and a register file.
Throughout this process, I made sure to conform to Verilog standards that allowed for my design to be synthesizable. This way I could incrementally test my design on the FPGA board using Quartus.
Step 2 – FSM Controller
Now, we have created the datapath which can perform various arithmetic and bitwise operations, however, we need a way to automate the process of setting control inputs to the datapth; this is where the FSM controller comes in. After defining 16 bit instructions, an instruction register feeds instructions to the controller, and the controller enables certain registers as is necessary.
Step 3 – Memory and I/O
In this step, I added functionality for memory-based instructions, specifically load and store operations. These instructions enable the RISC machine to interact with memory, allowing data to be read from and written to specific memory addresses.
Step 4 – Branches
In this step, I implemented branch instructions, which are crucial for controlling the flow of execution in a program. Branch instructions enable the RISC machine to make decisions and execute different parts of the code based on specific conditions.
Step 5 – Pipelining
In this step, I implemented pipelining to enhance the performance of the RISC machine by allowing multiple instructions to be processed simultaneously. Pipelining breaks down instruction execution into discrete stages, such as instruction fetch, decode, execute, memory access, and write-back, with each stage handled in parallel.